Project 4 (2016)

Trabajo Inglés
Universidad Universidad Politécnica de Cataluña (UPC)
Grado Ingeniería de Sistemas de Telecomunicación - 2º curso
Asignatura C.S.D. Circuits Sistemes Digitals
Año del apunte 2016
Páginas 13
Fecha de subida 29/09/2017
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DIGITAL CIRCUITS AND SYSTEMS (CSD) Cooperative group: G___________ Due date: ____________________ Project number: P________ Project name: ____________________________________________________ STATEMENT: My signature below indicates that I have (1) made an equitable contribution to the project as a member of the group, (2) read and fully agree with the content (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.
Cooperative group members (1) _______________________________________ (2) ________________________________________ (3) ______________________________________ Acknowledgement of individual(s) who assisted this group in completing this document (do not name the instructor): (1) _______________________ (2) _______________________ Today’s date and signatures: _______________________________________________________________ Table of content (each section in a different sheet of paper, use as many sheets as necessary).
1.
Specifications 2.
Planning 3.
Development of the Plan A 4.
Testing and verification of the Plan A 5.
Development of the Plan B 6.
Testing and verification of the Plan B Combinational circuits 1. Specifications EETAC – Digital Circuits and Systems 2. Planning Combinational circuits 3. Development VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; S(2) S(3) Z Cout entity Adder_subtractor_8bit is port( A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); OP : IN STD_LOGIC; Z, OV, Carry : OUT STD_LOGIC; R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); Chip2 : Onebit_adder of COMPONENT Adder_4bit IS PORT ( A,B : IN PORT MAP( Ai Bi => Ci => So Co ); => A(4), K(4), C(4), => W(4), => C(5) Chip3 : Onebit_adder STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout : OUT STD_LOGIC; Z : OUT STD_LOGIC -- Z = 0 when S(3..0) and C4 = 0; ); END COMPONENT; COMPONENT Onebit_adder IS PORT ( Ai,Bi, Ci : IN STD_LOGIC; So, Co W(2), W(3), Zero, C(4) ); end Adder_subtractor_8bit; architecture Behavioral Adder_subtractor_8bit is => => => => : OUT STD_LOGIC PORT MAP( Ai Bi => Ci => So Co ); => A(5), K(5), C(5), => W(5), => C(6) Chip4 : Onebit_adder PORT MAP( Ai Bi => Ci => So Co ); => A(6), K(6), C(6), => W(6), => C(7) Chip5 : Onebit_adder ); END COMPONENT; SIGNAL SIGNAL SIGNAL SIGNAL C : STD_LOGIC_VECTOR(8 DOWNTO 4); W : STD_LOGIC_VECTOR(7 DOWNTO 0); K : STD_LOGIC_VECTOR(7 DOWNTO 0); Zero : STD_LOGIC; begin Chip1 : Adder_4bit PORT MAP ( -- from component name port name A(0) => A(0), A(1) => A(1), A(2) => A(2), A(3) => A(3), B(0) => K(0), B(1) => K(1), B(2) => K(2), B(3) => K(3), Cin => OP, S(0) => W(0), S(1) => W(1), => to signal or PORT MAP( Ai Bi => Ci => So Co ); => A(7), K(7), C(7), => W(7), => C(8) Carry <= C(8); OV <= C(7) XOR C(8); Z <= Zero AND (NOT(W(4) OR (W(5) OR (W(6) OR (W(7) OR C(8)))))); K(0) <= B(0) XOR OP; K(1) <= B(1) XOR OP; K(2) <= B(2) XOR OP; K(3) <= B(3) XOR OP; K(4) <= B(4) XOR OP; K(5) <= B(5) XOR OP; K(6) <= B(6) XOR OP; K(7) <= B(7) XOR OP; R <= W; end Behavioral; EETAC – Digital Circuits and Systems ONE BIT ADDER VHDL CODE LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY ONEBIT_ADDER IS PORT ( Ai,Bi, Ci : IN STD_LOGIC; So, Co : OUT STD_LOGIC ); END ONEBIT_ADDER; ARCHITECTURE truth_table OF ONEBIT_ADDER IS -- The translation of this schematic: -- http://digsys.upc.es/csd/P03/P3_T/Beh/P3_fig_1.jpg SIGNAL SIGNAL Y_OUT : STD_LOGIC_VECTOR (1 downto 0); X_IN : STD_LOGIC_VECTOR (2 downto 0); BEGIN PROCESS (X_IN) BEGIN CASE X_IN IS -- Ai Bi Ci Co So -- -------- ------WHEN "000" => Y_OUT <= "00"; WHEN "001" => Y_OUT <= "01"; WHEN "010" => Y_OUT <= "01"; WHEN "011" => Y_OUT <= "10"; WHEN "100" => Y_OUT <= "01"; WHEN "101" => Y_OUT <= "10"; WHEN "110" => Y_OUT <= "10"; WHEN Others => -- The last combination: 1+1+1 = "11" Y_OUT <= "11"; END CASE; END PROCESS; -- Extra logic (simple buffers in this case) X_IN(2) <= Ai; X_IN(1) <= Bi; X_IN(0) <= Ci; Co <= Y_OUT(1); So <= Y_OUT(0); END truth_table; EETAC – Digital Circuits and Systems FOUR BIT ADDER VHDL CODE LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; Ai => A(0), Bi => B(0), Ci => Cin, So => Y(0), Co => C1 ENTITY Adder_4bit IS PORT ( A,B : IN ); STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout : OUT STD_LOGIC; Z : OUT STD_LOGIC -- Z = 0 when S(3..0) and C4 = 0; ); END Adder_4bit; ARCHITECTURE hierarchical_structure OF Adder_4bit IS -- The elemental component to be used: COMPONENT ONEBIT_ADDER IS Chip_1 : ONEBIT_ADDER PORT MAP ( -- from component name to signal or port name Ai => A(1), Bi => B(1), Ci => C1, So => Y(1), Co => C2 ); Chip_2 : ONEBIT_ADDER PORT MAP ( -- from component name => to signal or port name Ai => A(2), Bi => B(2), Ci => C2, So => Y(2), Co => C3 PORT ( Ai,Bi, Ci : IN STD_LOGIC; So, Co ); : OUT STD_LOGIC END COMPONENT; -- Signals SIGNAL C1, C2, C3, C4 : STD_LOGIC; -- The wires to connect 1-bit modules together SIGNAL Y : STD_LOGIC_VECTOR (3 DOWNTO 0); => ); Chip_3 : ONEBIT_ADDER PORT MAP ( -- from component name => to signal or port name Ai => A(3), Bi => B(3), Ci => C3, So => Y(3), Co => C4 ); -- Other circuits and equations: BEGIN S <= Y; -- Instantiation of up to 4 basic 1-bit adders: Z <= NOT (Y(3) OR Y(2) OR Y(1) OR Y(0) OR C4 ); Cout <= C4; Chip_0 : ONEBIT_ADDER PORT MAP ( -- from component name signal or port name END hierarchical_structure; => to EETAC – Digital Circuits and Systems Combinational circuits 4. Testing and verification TEST BENCH VHDL CODE LIBRARY ieee; USE ieee.std_logic_1164.ALL; constant min_pulse : time := 10 ms; BEGIN ENTITY Adder_subtractor_8bit_tb IS END Adder_subtractor_8bit_tb; ARCHITECTURE behavior Adder_subtractor_8bit_tb IS OF -- Component Declaration for the Unit Under Test (UUT) COMPONENT Adder_subtractor_8bit PORT( A : IN std_logic_vector(7 downto 0); B : IN std_logic_vector(7 downto -- Instantiate the Unit Under Test (UUT) uut: Adder_subtractor_8bit PORT MAP ( A => A, B => B, OP => OP, Z => Z, OV => OV, Carry => Carry, R => R ); -- Stimulus process tb: process 0); OP : IN std_logic; Z : OUT std_logic; OV : OUT std_logic; Carry : OUT std_logic; R : OUT std_logic_vector(7 downto begin A <= "00000000"; B <= "00000000"; OP <= '0'; wait for min_pulse; 0) ); END COMPONENT; --Inputs signal A : std_logic_vector(7 downto 0) := (others => '0'); signal B : std_logic_vector(7 downto 0) := (others => '0'); signal OP : std_logic := '0'; --Outputs signal Z : std_logic; signal OV : std_logic; signal Carry : std_logic; signal R : std_logic_vector(7 downto 0); -- No clocks detected in port list.
A <= "00000100"; B <= "00001100"; wait for min_pulse; A <= "00000101"; B <= "00000001"; OP <= '1'; wait for min_pulse; A <= "01100000"; B <= "01100000"; OP <= '0'; wait; end process; END; Combinational circuits Data Sheet report: ----------------All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ A<0> |Carry | 13.415| A<0> |OV | 12.850| A<0> |R<0> | 6.608| A<0> |R<1> | 7.620| A<0> |R<2> | 9.042| A<0> |R<3> | 9.640| A<0> |R<4> | 10.890| A<0> |R<5> | 11.990| A<0> |R<6> | 12.362| A<0> |R<7> | 13.674| A<0> |Z | 15.036| A<1> |Carry | 13.682| A<1> |OV | 13.117| A<1> |R<1> | 7.713| A<1> |R<2> | 9.309| A<1> |R<3> | 9.907| A<1> |R<4> | 11.157| A<1> |R<5> | 12.257| A<1> |R<6> | 12.629| A<1> |R<7> | 13.941| A<1> |Z | 15.303| A<2> |Carry | 11.937| A<2> |OV | 11.372| A<2> |R<2> | 7.375| A<2> |R<3> | 8.162| A<2> |R<4> | 9.412| A<2> |R<5> | 10.512| A<2> |R<6> | 10.884| A<2> |R<7> | 12.196| A<2> |Z | 13.558| A<3> |Carry | 10.863| A<3> |OV | 10.298| A<3> |R<3> | 6.909| A<3> |R<4> | 8.338| A<3> |R<5> | 9.438| A<3> |R<6> | 9.810| A<3> |R<7> | 11.122| A<3> |Z | 12.484| A<4> |Carry | 9.652| A<4> |OV | 9.087| A<4> |R<4> | 7.873| A<4> |R<5> | 8.227| A<4> |R<6> | 8.599| A<4> |R<7> | 9.911| A<4> |Z | 11.273| A<5> |Carry | 8.859| A<5> |OV | 8.294| A<5> |R<5> | 7.265| A<5> |R<6> | 7.806| A<5> |R<7> | 9.118| A<5> |Z | 10.480| A<6> |Carry | 7.923| A<6> |OV | 7.358| A<6> |R<6> | 7.334| A<6> |R<7> | 8.182| A<6> |Z | 9.544| A<7> |Carry | 7.027| A<7> |OV | 6.462| A<7> |R<7> | 7.119| A<7> |Z | 8.648| B<0> |Carry | 13.559| B<0> |OV | 12.994| B<0> |R<0> | 7.019| B<0> |R<1> | 7.764| B<0> |R<2> | 9.186| B<0> |R<3> | 9.784| B<0> |R<4> | 11.034| B<0> |R<5> | 12.134| B<0> |R<6> | 12.506| B<0> |R<7> | 13.818| B<0> |Z | 15.180| B<1> |Carry | 12.821| B<1> |OV | 12.256| B<1> |R<1> | 6.797| B<1> |R<2> | 8.448| B<1> |R<3> | 9.046| B<1> |R<4> | 10.296| B<1> |R<5> | 11.396| B<1> |R<6> | 11.768| B<1> |R<7> | 13.080| B<1> |Z | 14.442| B<2> |Carry | 11.422| B<2> |OV | 10.857| B<2> |R<2> | 7.127| B<2> |R<3> | 7.647| B<2> |R<4> | 8.897| B<2> |R<5> | 9.997| B<2> |R<6> | 10.369| B<2> |R<7> | 11.681| B<2> |Z | 13.043| B<3> |Carry | 10.613| B<3> |OV | 10.048| B<3> |R<3> | 6.669| B<3> |R<4> | 8.088| B<3> |R<5> | 9.188| B<3> |R<6> | 9.560| B<3> |R<7> | 10.872| B<3> |Z | 12.234| B<4> |Carry | 9.484| B<4> |OV | 8.919| B<4> |R<4> | 7.076| B<4> |R<5> | 8.059| B<4> |R<6> | 8.431| B<4> |R<7> | 9.743| B<4> |Z | 11.105| B<5> |Carry | 8.510| B<5> |OV | 7.945| B<5> |R<5> | 6.906| B<5> |R<6> | 7.457| B<5> |R<7> | 8.769| B<5> |Z | 10.131| B<6> |Carry | 7.791| B<6> |OV | 7.226| B<6> |R<6> | 6.793| B<6> |R<7> | 8.050| B<6> |Z | 9.412| B<7> |Carry | 7.453| B<7> |OV | 6.888| B<7> |R<7> | 7.724| B<7> |Z | 9.074| OP |Carry | 13.958| OP |OV | 13.393| OP |R<1> | 8.163| OP |R<2> | 9.585| OP |R<3> | 10.183| OP |R<4> | 11.433| OP |R<5> | 12.533| OP |R<6> | 12.905| OP |R<7> | 14.217| OP |Z | 15.579| ---------------+---------------+---------+ EETAC – Digital Circuits and Systems Combinational circuits ...

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